Key Features
Industry First Platform FPGA Solution
IP-Immersion Architecture
Densities from 40K to 8M system gates
420 MHz internal clock speed (Advance Data)
840+ Mb/s I/O (Advance Data)
SelectRAM
Memory Hierarchy
3 Mb of dual-port RAM in 18 Kbit block SelectRAM resources
Up to 1.5 Mb of distributed SelectRAM resources
High-Performance Interfaces to External Memory
DRAM interfaces · SDR / DDR SDRAM · Network FCRAM · Reduced Latency DRAM
SRAM interfaces · SDR / DDR SRAM · QDR
SRAM
CAM interfaces
Arithmetic Functions
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Flexible Logic Resources
Up to 93,184 internal registers / latches with Clock Enable
Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and sum-of-products support
Internal 3-state bussing
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